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Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

EURASIP Journal on Advances in Signal Processing volume 2007, Article number: 067360 (2007) Cite this article

Abstract

It has recently been shown that thse-dimensional reduced adder graph (RAG-) technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG- technique can be applied to these algorithms. This RAG- DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp- algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Florida State University, 2525 Pottsdamer Street, Tallahassee, FL, 32310-6046, USA

    Uwe Meyer-Bäse & Hariharan Natarajan

  2. School of Surveying and Spatial Information Systems, University of New South Wales, Sydney, 2052, Australia

    Andrew G Dempster

Authors
  1. Uwe Meyer-Bäse
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  2. Hariharan Natarajan
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  3. Andrew G Dempster
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Correspondence to Uwe Meyer-Bäse.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://doi.org/creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Meyer-Bäse, U., Natarajan, H. & Dempster, A.G. Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique. EURASIP J. Adv. Signal Process. 2007, 067360 (2007). https://doi.org/10.1155/2007/67360

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