Skip to main content


We're creating a new version of this page. See preview

  • Research Article
  • Open Access

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

  • 1Email author,
  • 2,
  • 1,
  • 1, 3, 4 and
  • 5
EURASIP Journal on Advances in Signal Processing20072007:084078

  • Received: 14 September 2006
  • Accepted: 23 April 2007
  • Published:


The design of increasingly complex and concurrent multimedia systems requires a description at a higher abstraction level. Using an appropriate model of computation helps to reason about the system and enables design time analysis methods. The nature of multimedia processing matches in many cases well with cyclo-static dataflow (CSDF), making it a suitable model. However, channels in an implementation often use for cost reasons a kind of shared buffer that cannot be directly described in CSDF. This paper shows how such implementation specific aspects can be expressed in CSDF without the need for extensions. Consequently, the CSDF graph remains completely analyzable and allows reasoning about its temporal behavior. The obtained relation between model and implementation enables a buffer capacity analysis on the model while assuring the throughput of the final implementation. The capabilities of the approach are demonstrated by analyzing the temporal behavior of an MPEG-4 video encoder with a CSDF graph.


  • Quantum Information
  • Suitable Model
  • Buffer Capacity
  • Temporal Behavior
  • Design Time

Authors’ Affiliations

Nomadic Embedded Systems (NES), Interuniversity Micro Electronics Centre (IMEC), Kapeldreef 75, Leuven, 3001, Belgium
NXP Research, Systems and Circuits, Prof. Holstlaan 4, AE Eindhoven, 5656, The Netherlands
Department of Electrical Engineering, Katholieke Universiteit Leuven (KU-Leuven), Leuven, 3001, Belgium
Department of Electrical Engineering, Vrije Universiteit Brussel (VUB), Brussels, 1050, Belgium
Faculty of Electrical Engineering, Technical University Eindhoven, Den Dolech 2, AZ, Eindhoven, 5612, The Netherlands


  1. Sriram S, Bhattacharyya SS: Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker, New York, NY, USA; 2000.Google Scholar
  2. Bilsen G, Engels M, Lauwereins R, Peperstraete J: Cyclo-static dataflow. IEEE Transactions on Signal Processing 1996,44(2):397-408. 10.1109/78.485935View ArticleGoogle Scholar
  3. Davare A, Zhu Q, Moondanos J, Sangiovanni-Vincentelli A: JPEG encoding on the intel MXP5800: a platform-based design case study. Proceedings of the 3rd IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTMED '05), September 2005, New York, NY, USA 89–94.Google Scholar
  4. Hwang H, Oh T, Jung H, Ha S: Conversion of reference C code to dataflow model H.264 encoder case study. Proceedings of the Asia and South Pacific Design Automation Conference (DAC '06), January 2006, Yokohama, Japan 152–157.Google Scholar
  5. Haim F, Sen M, Ko D-I, Bhattacharyya SS, Wolf W: Mapping multimedia applications onto configurable hardware with parameterized cyclo-static dataflow graphs. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '06), May 2006, Toulouse, France 3: 1052–1055.Google Scholar
  6. Stuijk S, Geilen M, Basten T: Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. Proceedings of the 43rd Design Automation Conference (DAC '06), July 2006, San Francisco, Calif, USA 899–904.Google Scholar
  7. Park C, Jung J, Ha S: Extended synchronous dataflow for efficient DSP system prototyping. Design Automation for Embedded Systems 2002,6(3):295-322. 10.1023/A:1014070804761View ArticleGoogle Scholar
  8. Edwards S, Lavagno L, Lee EA, Sangiovanni-Vincentelli A: Design of embedded systems: formal models, validation, and synthesis. Proceedings of the IEEE 1997,85(3):366-390. 10.1109/5.558710View ArticleGoogle Scholar
  9. Lee EA, Parks TM: Dataflow process networks. Proceedings of the IEEE 1995,83(5):773-801. 10.1109/5.381846View ArticleGoogle Scholar
  10. Bhattacharyya SS, Sriram S, Lee EA: Resynchronization for multiprocessor DSP systems. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 2000,47(11):1597-1609. 10.1109/81.895327MathSciNetView ArticleGoogle Scholar
  11. Lee EA, Messerschmitt DG: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers 1987,36(1):24-35.View ArticleGoogle Scholar
  12. Poplavko P, Basten T, Bekooij M, van Meerbergen J, Mesman B: Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES '03), October-November 2003, San Jose, Calif, USA 63–72.View ArticleGoogle Scholar
  13. Wiggers MH, Bekooij M, Jansen P, Smit G: Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure. Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), October 2006, Seoul, Korea 10–15.View ArticleGoogle Scholar
  14. Wiggers MH, Bekooij M, Jansen P, Smit G: Efficient computation of buffer capacities for cyclo-static real-time systems with back-pressure. Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS '07), April 2007, Bellevue, Wash, USA 281–292.View ArticleGoogle Scholar
  15. Teich J, Bhattacharyya SS: Analysis of dataflow programs with interval-limited data-rates. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 2006,43(2-3):247-258. 10.1007/s11265-006-7274-2View ArticleGoogle Scholar
  16. Richardson IEG: H.264 and MPEG-4 Video Compression: Video Coding for Next-Generation Multimedia. John Wiley & Sons, New York, NY, USA; 2003.View ArticleGoogle Scholar
  17. Murthy PK, Bhattacharyya SS: Shared buffer implementations of signal processing systems using lifetime analysis techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001,20(2):177-198. 10.1109/43.908427View ArticleGoogle Scholar
  18. Oh H, Ha S: Memory-optimized software synthesis from dataflow program graphs with large size data samples. EURASIP Journal on Applied Signal Processing 2003,2003(6):514-529. 10.1155/S1110865703212130MATHGoogle Scholar
  19. Information technology—generic coding of audio-visual objects—part 2: visual ISO/IEC 14496-2:2004, June 2004Google Scholar
  20. Denolf K, Chirila-Rus A, Verkest D: Low-power MPEG-4 video encoder design. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '05), November 2005, Athens, Greece 284–289.Google Scholar


© Kristof Denolf et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.