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A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding


Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18m CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45, and yields a throughput rate of 20 M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.


  1. Li H, Zhang CN: Low-complexity versatile finite field multiplier in normal basis. EURASIP Journal on Applied Signal Processing 2002,2002(9):954-960. 10.1155/S111086570220414X

    MathSciNet  MATH  Google Scholar 

  2. Bigdeli A, Biglari-Abhari M, Salcic Z, Lai YT: A new pipelined systolic array-based architecture for matrix inversion in FPGAs with Kalman filter case study. EURASIP Journal on Applied Signal Processing 2006, 2006: 12 pages.

    Google Scholar 

  3. Chen L-H, Chen OT-C: A low-complexity and high-speed Booth-algorithm FIR architecture. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '01), May 2001, Sydney, NSW, Australia 4: 338–341.

    Google Scholar 

  4. Chen L-H, Chen OT-C: A hardware-efficient FIR architecture with input-data and tap folding. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), May 2005, Kobe, Japan 1: 544–547.

    Article  Google Scholar 

  5. Edwards B, Corry A, Weste N, Greenberg C: A single-chip video ghost canceller. IEEE Journal of Solid-State Circuits 1993,28(3):379-383. 10.1109/4.210007

    Article  Google Scholar 

  6. Wang CH, Erdogan AT, Arslan T: High throughput and low power FIR filtering IP cores. Proceedings of IEEE International SOC Conference, September 2004, Santa Clara, Calif, USA 127–130.

    Google Scholar 

  7. Meier SR, Schobinger M: Time-sharing architectures for FIR filter structures. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '00), June 2000, Istanbul, Turkey 6: 3307–3310.

    Google Scholar 

  8. Saponara S, Fanucci L, Terreni P: Design of a low-power VLSI macrocell for nonlinear adaptive video noise reduction. EURASIP Journal on Applied Signal Processing 2004,2004(12):1921-1930. 10.1155/S1110865704403035

    Google Scholar 

  9. Pao S, Khoo K-Y, Willson AN Jr.: A programmable FIR filter for TV ghost cancellation. Proceedings of the 39th IEEE Midwest Symposium on Circuits and Systems (MWSCAS '96), August 1996, Ames, Iowa, USA 1: 133–136.

    Article  Google Scholar 

  10. Chen OT-C, Liu W-L: An FIR processor with programmable dynamic data ranges. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2000,8(4):440-446.

    Article  Google Scholar 

  11. Dawoud DS: Realization of pipelined multiplier-free FIR digital filter. Proceedings of the 5th IEEE AFRICON Conference on Electrotechnological Services for Africa (AFRICON '99), September-October 1999, Cape Town, South Africa 1: 335–338.

    Google Scholar 

  12. Koren I: Computer Arithmetic Algorithms. Prentice-Hall, Englewood Cliffs, NJ, USA; 1993.

    MATH  Google Scholar 

  13. Pirsch P: Architectures for Digital Signal Processing. John Wiley & Sons, New York, NY, USA; 1998.

    Google Scholar 

  14. Chen L-H, Liu W-L, Chen OT-C: Determination of radix numbers of the Booth algorithm for the optimized programmable FIR architecture. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '00), May 2000, Geneva, Switzerland 2: 345–348.

    Google Scholar 

  15. TSMC 0.18m Process 1.8 Volt SAGE- Standard Cell Library Databook Artisan components, September 2003

  16. Kim K-S, Lee K: Low-power and area-efficient FIR filter implementation suitable for multiple taps. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2003,11(1):150-153.

    Article  Google Scholar 

  17. Nicol CJ, Larsson P, Azadet K, O'Neill JH: A low-power 128-tap digital adaptive equalizer for broadband modems. IEEE Journal of Solid-State Circuits 1997,32(11):1777-1789. 10.1109/4.641700

    Article  Google Scholar 

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Correspondence to Oscal T.-C. Chen.

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Chen, O.TC., Chen, LH. A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding. EURASIP J. Adv. Signal Process. 2007, 092523 (2007).

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