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Real-Time Target Detection Architecture Based on Reduced Complexity Hyperspectral Processing

Abstract

This paper presents a real-time target detection architecture for hyperspectral image processing. The architecture is based on a reduced complexity algorithm for high-throughput applications.We propose an efficient pipelined processing element architecture and a scalable multiple-processing element architecture by exploiting data partitioning. We present a processing unit modeling based on the data reduction algorithm in hyperspectral image processing and propose computing structure, that is, to optimize memory usage and eliminates memory bottleneck. We investigate the interconnection topology for the multipleprocessing element architecture to improve the speed. The proposed architecture is designed and implemented in FPGA to illustrate the relationship between hardware complexity and execution throughput of hyperspectral image processing for target detection.

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Correspondence to Sangjin Hong.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Park, KS., Cho, S.H., Hong, S. et al. Real-Time Target Detection Architecture Based on Reduced Complexity Hyperspectral Processing. EURASIP J. Adv. Signal Process. 2008, 438051 (2008). https://doi.org/10.1155/2008/438051

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Keywords

  • Processing Element
  • Target Detection
  • Memory Usage
  • Reduction Algorithm
  • Unit Modeling