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  • Research Article
  • Open Access

Real-Time Target Detection Architecture Based on Reduced Complexity Hyperspectral Processing

  • 1,
  • 1,
  • 1Email author and
  • 2
EURASIP Journal on Advances in Signal Processing20082008:438051

https://doi.org/10.1155/2008/438051

  • Received: 30 May 2007
  • Accepted: 28 March 2008
  • Published:

Abstract

This paper presents a real-time target detection architecture for hyperspectral image processing. The architecture is based on a reduced complexity algorithm for high-throughput applications.We propose an efficient pipelined processing element architecture and a scalable multiple-processing element architecture by exploiting data partitioning. We present a processing unit modeling based on the data reduction algorithm in hyperspectral image processing and propose computing structure, that is, to optimize memory usage and eliminates memory bottleneck. We investigate the interconnection topology for the multipleprocessing element architecture to improve the speed. The proposed architecture is designed and implemented in FPGA to illustrate the relationship between hardware complexity and execution throughput of hyperspectral image processing for target detection.

Keywords

  • Processing Element
  • Target Detection
  • Memory Usage
  • Reduction Algorithm
  • Unit Modeling

Publisher note

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Authors’ Affiliations

(1)
Mobile Systems Design Laboratory, Department of Electrical and Computer Engineering, College of Engineering and Apllied Sciences, Stony Brook University-SUNY, Stony Brook, NY 11794-2350, USA
(2)
Division of Electrical & Computer Engineering, College of Information Technology, Ajou University, Suwon, 443-749, South Korea

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