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  • Research Article
  • Open Access

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

  • 1Email author,
  • 1,
  • 1,
  • 2 and
  • 2
EURASIP Journal on Advances in Signal Processing20092009:127630

https://doi.org/10.1155/2009/127630

  • Received: 25 September 2008
  • Accepted: 30 January 2009
  • Published:

Abstract

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A cell parallel analog test array for reference-shift with a maximum block-size of , as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13  m CMOS technology.

Keywords

  • Motion Estimation
  • Neighborhood Connection
  • Silicon Area
  • Test Array
  • Search Motion

Publisher note

To access the full article, please see PDF.

Authors’ Affiliations

(1)
Department of Information Technology, University of Turku, 20014 Turku, Finland
(2)
Electronic Circuit Design Laboratory, Helsinki University of Technology, P.O. Box 300, 02015 Espoo, Finland

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