Open Access

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

  • Jonne Poikonen1Email author,
  • Mika Laiho1,
  • Ari Paasio1,
  • Lauri Koskinen2 and
  • Kari Halonen2
EURASIP Journal on Advances in Signal Processing20092009:127630

https://doi.org/10.1155/2009/127630

Received: 25 September 2008

Accepted: 30 January 2009

Published: 4 March 2009

Abstract

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A cell parallel analog test array for reference-shift with a maximum block-size of , as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13  m CMOS technology.

Keywords

Motion EstimationNeighborhood ConnectionSilicon AreaTest ArraySearch Motion

Publisher note

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Authors’ Affiliations

(1)
Department of Information Technology, University of Turku, Turku, Finland
(2)
Electronic Circuit Design Laboratory, Helsinki University of Technology, Espoo, Finland

Copyright

© Jonne Poikonen et al. 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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