- Research Article
- Open Access
APRON: A Cellular Processor Array Simulation and Hardware Design Tool
EURASIP Journal on Advances in Signal Processing volume 2009, Article number: 751687 (2009)
We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.
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Barr, D.R., Dudek, P. APRON: A Cellular Processor Array Simulation and Hardware Design Tool. EURASIP J. Adv. Signal Process. 2009, 751687 (2009). https://doi.org/10.1155/2009/751687
- Hardware Architecture
- Software Environment
- Hardware Design
- Publisher Note
- Processor Array