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  • Research Article
  • Open Access

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

EURASIP Journal on Advances in Signal Processing20092009:751687

https://doi.org/10.1155/2009/751687

Received: 12 September 2008

Accepted: 21 March 2009

Published: 7 May 2009

Abstract

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Keywords

  • Hardware Architecture
  • Software Environment
  • Hardware Design
  • Publisher Note
  • Processor Array

Publisher note

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Authors’ Affiliations

(1)
School of Electrical and Electronic Engineering, The University of Manchester, Manchester, UK

Copyright

© D. R. W. Barr and P. Dudek. 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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