Table 1 FPGA versus CPU comparison for iris match execution.
From: Comparing an FPGA to a Cell for an Image Processing Application
|  | Optimized Xeon Code on PS3 | CELL (with 6 SPEs) | Cyclone-II EP2C35 (50 MHz) | Cyclone-II estimated @ 100 MHz | Stratix IV estimated @ 500 MHz |
|---|---|---|---|---|---|
Time per match (ns) | 383 ns | 50 ns | 20 ns | 10 ns (est) | 2 ns (est) |
Speedup over Xeon | n/a | 7.66 | 19.15 | 38.3 | 191.5 |
% usage of chip | n/a | n/a | 73% | n/a | 7.3% (est) |