Table 2 Summary of resource utilization for the FPGA-based implementation of the PPI algorithm.
Component | Number of skewers | Number of slice flip flops | Number of 4 input LUTs | Number of slices | Percentage of total | Maximum operation frequency (MHz) |
|---|---|---|---|---|---|---|
Systolic Array | 20 | 2240 | 3865 | 2085 | 15.22 | 187 |
40 | 4480 | 7728 | 4170 | 30.44 | 187 | |
60 | 6720 | 11591 | 6254 | 45.66 | 187 | |
80 | 8960 | 15454 | 8339 | 60.88 | 187 | |
100 | 11200 | 19317 | 10423 | 76.1 | 187 | |
Random Generation Module | 20 | 40 | 120 | 58 | 0 | 664 |
40 | 80 | 240 | 115 | 0.42 | 664 | |
60 | 120 | 360 | 173 | 0.84 | 664 | |
80 | 160 | 480 | 230 | 1.68 | 664 | |
100 | 200 | 600 | 288 | 2.1 | 664 | |
RS232 Transmitter | — | 69 | 128 | 71 | 0.52 | 208 |
DMA Controller | — | 170 | 531 | 367 | 2.68 | 102 |