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  • Research Article
  • Open Access

Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

EURASIP Journal on Advances in Signal Processing20102011:639043

https://doi.org/10.1155/2011/639043

  • Received: 31 May 2010
  • Accepted: 22 December 2010
  • Published:

Abstract

Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic computational forms. The proposed solution has been specially designed to have good fixed-point error performances that have been exploited to further reduce the hardware complexity and power consumption. It leads to a ROM based VLSI kernel with good quantization properties. A parallel VLSI algorithm and architecture with a good fixed point implementation appropriate for a memory-based implementation have been obtained. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form. They can be further efficiently merged into a single array using an appropriate hardware sharing technique. A highly efficient VLSI chip can be thus obtained with appealing features as good architectural topology, processing speed, hardware complexity and I/O costs. Moreover, the proposed solution substantially reduces the hardware overhead involved by the pre-processing stage that for short length DCT consumes an important percentage of the chip area.

Keywords

  • Systolic Array
  • Hardware Complexity
  • Hardware Overhead
  • Parallel VLSI
  • VLSI Chip

Publisher note

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Authors’ Affiliations

(1)
Faculty of Electronics, Telecommunications and Information Technology, Technical University "Gh. Asachi", B-dul Carol I, No.11, 6600 Iasi, Romania

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