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Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design

Abstract

High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on uniform-width resources according to the worst-case data requirements, that is, the largest word length. HLS techniques have been reviewed for the last few years to benefit from multiple word-length fixed point description of the algorithms to be implemented. Aims were to save design area and power consumption. Unfortunately, data-width timing issues over the operation's latency have not been taken into account accurately. In this paper, an HLS process that takes care of the delay of the operators according to the data width is presented. Experimental results show that our approach achieves significant design latency saving or area decrease compared to a conventional synthesis.

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Correspondence to Bertrand Le Gal.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Le Gal, B., Casseau, E. Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Signal Process. 2011, 927670 (2011). https://doi.org/10.1155/2011/927670

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Keywords

  • Word Length
  • Timing Issue
  • Design Time
  • Publisher Note
  • Significant Design