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  • Research Article
  • Open Access

Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design

EURASIP Journal on Advances in Signal Processing20112011:927670

https://doi.org/10.1155/2011/927670

  • Received: 28 June 2010
  • Accepted: 19 January 2011
  • Published:

Abstract

High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on uniform-width resources according to the worst-case data requirements, that is, the largest word length. HLS techniques have been reviewed for the last few years to benefit from multiple word-length fixed point description of the algorithms to be implemented. Aims were to save design area and power consumption. Unfortunately, data-width timing issues over the operation's latency have not been taken into account accurately. In this paper, an HLS process that takes care of the delay of the operators according to the data width is presented. Experimental results show that our approach achieves significant design latency saving or area decrease compared to a conventional synthesis.

Keywords

  • Word Length
  • Timing Issue
  • Design Time
  • Publisher Note
  • Significant Design

Publisher note

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Authors’ Affiliations

(1)
IMS Laboratory UMR-CNRS 5218, Polytechnic Institute of Bordeaux (IPB), University of Bordeaux, 33405 Talence CEDEX, France
(2)
IRISA-CAIRN laboratory, ENSSAT Engineering School, University of Rennes 1, BP 80518, 22305 Lannion CEDEX, France

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