FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
© Torres-Huitzil and Arias-Estrada 2005
Received: 13 September 2003
Published: 22 May 2005
Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to , but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of GOPs at a 60 MHz clock frequency and a processing time of milliseconds for generic window-based operators on gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.