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Cost-Effective Video Filtering Solution for Real-Time Vision Systems

Abstract

This paper presents an efficient video filtering scheme and its implementation in a field-programmable logic device (FPLD). Since the proposed nonlinear, spatiotemporal filtering scheme is based on order statistics, its efficient implementation benefits from a bit-serial realization. The utilization of both the spatial and temporal correlation characteristics of the processed video significantly increases the computational demands on this solution, and thus, implementation becomes a significant challenge. Simulation studies reported in this paper indicate that the proposed pipelined bit-serial FPLD filtering solution can achieve speeds of up to 97.6 Mpixels/s and consumes 1700 to 2700 logic cells for the speed-optimized and area-optimized versions, respectively. Thus, the filter area represents only 6.6 to 10.5% of the Altera STRATIX EP1S25 device available on the Altera Stratix DSP evaluation board, which has been used to implement a prototype of the entire real-time vision system. As such, the proposed adaptive video filtering scheme is both practical and attractive for real-time machine vision and surveillance systems as well as conventional video and multimedia applications.

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Correspondence to Viktor Fischer.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Fischer, V., Lukac, R. & Martin, K. Cost-Effective Video Filtering Solution for Real-Time Vision Systems. EURASIP J. Adv. Signal Process. 2005, 568069 (2005). https://doi.org/10.1155/ASP.2005.2026

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  • DOI: https://doi.org/10.1155/ASP.2005.2026

Keywords and phrases

  • VHDL implementation
  • FPLD
  • bit-serial approach
  • pipelined solution
  • video filtering and enhancement
  • nonlinear adaptive filter design