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Bit Manipulation Accelerator for Communication Systems Digital Signal Processor


This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about for scrambling, convolutional encoding, and interleaving compared with existing DSPs.

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Correspondence to Sug H. Jeong.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Jeong, S.H., Sunwoo, M.H. & Oh, S.K. Bit Manipulation Accelerator for Communication Systems Digital Signal Processor. EURASIP J. Adv. Signal Process. 2005, 793614 (2005).

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