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Open Access

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

EURASIP Journal on Advances in Signal Processing20052005:793614

Received: 30 January 2004

Published: 21 September 2005


This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about for scrambling, convolutional encoding, and interleaving compared with existing DSPs.

Keywords and phrases

bit manipulationapplication-specific DSPVLSI architecture

Authors’ Affiliations

School of Electrical and Computer Engineering, Ajou University, Suwon, Korea


© Jeong et al. 2005