Skip to main content

Multimedia Terminal System-on-Chip Design and Simulation

Abstract

This paper proposes a design approach based on integrated architectural and system-on-chip (SoC) simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW) digital signal processors (DSPs), the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA) simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.

Author information

Affiliations

Authors

Corresponding author

Correspondence to Ivano Barbieri.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Barbieri, I., Bariani, M., Scotto, A. et al. Multimedia Terminal System-on-Chip Design and Simulation. EURASIP J. Adv. Signal Process. 2005, 650749 (2005). https://doi.org/10.1155/ASP.2005.2694

Download citation

Keywords and phrases

  • system-on-chip
  • multimedia
  • HW-SW codesign
  • DSP
  • simulation
  • VLIW