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Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm


Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multisensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkola's BSS algorithm for audio signals based on ICA (independent component analysis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented. Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given.

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Correspondence to Charayaphan Charoensak.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Charoensak, C., Sattar, F. Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm. EURASIP J. Adv. Signal Process. 2005, 173453 (2005).

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Keywords and phrases:

  • ICA
  • BSS
  • codesign
  • FPGA