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  • Research Article
  • Open Access

Object Recognition System-on-Chip Using the Support Vector Machines

  • 1Email author,
  • 2,
  • 1,
  • 2 and
  • 2
EURASIP Journal on Advances in Signal Processing20052005:941303

https://doi.org/10.1155/ASP.2005.993

  • Received: 16 September 2003
  • Published:

Abstract

The first aim of this work is to propose the design of a system-on-chip (SoC) platform dedicated to digital image and signal processing, which is tuned to implement efficiently multiply-and-accumulate (MAC) vector/matrix operations. The second aim of this work is to implement a recent promising neural network method, namely, the support vector machine (SVM) used for real-time object recognition, in order to build a vision machine. With such a reconfigurable and programmable SoC platform, it is possible to implement any SVM function dedicated to any object recognition problem. The final aim is to obtain an automatic reconfiguration of the SoC platform, based on the results of the learning phase on an objects' database, which makes it possible to recognize practically any object without manual programming. Recognition can be of any kind that is from image to signal data. Such a system is a general-purpose automatic classifier. Many applications can be considered as a classification problem, but are usually treated specifically in order to optimize the cost of the implemented solution. The cost of our approach is more important than a dedicated one, but in a near future, hundreds of millions of gates will be common and affordable compared to the design cost. What we are proposing here is a general-purpose classification neural network implemented on a reconfigurable SoC platform. The first version presented here is limited in size and thus in object recognition performances, but can be easily upgraded according to technology improvements.

Keywords and phrases

  • parallel architecture
  • pattern recognition
  • support vector machines
  • hardware design language
  • systems-on-programmable-chip and system-on-chip platforms

Authors’ Affiliations

(1)
Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, 7 avenue du Colonel Roche, Toulouse Cedex 4, 31077, France
(2)
The Rennes Institute of Electronics and Telecommunications (IETR) (UMR CNRS 6164), INSA, 20 avenue des Buttes de Coësmes, Rennes Cedex, 35053, France

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