Skip to main content
EURASIP Journal on Advances in Signal Processing
Download PDF
  • Research Article
  • Open access
  • Published:

FPGA Prototyping of RNN Decoder for Convolutional Codes

EURASIP Journal on Advances in Signal Processing volume 2006, Article number: 015640 (2006) Cite this article

Abstract

This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.

References

  1. Ibnkahla M: Applications of neural networks to digital communications—a survey. Signal Processing 2000, 80(7):1185–1215. 10.1016/S0165-1684(00)00030-X

    Article  Google Scholar 

  2. Bruck J, Blaum M:Neural networks, error-correcting codes, and polynomials over the binary-cube. IEEE Transactions on Information Theory 1989, 35(5):976–987. 10.1109/18.42215

    Article  MathSciNet  Google Scholar 

  3. Ciocoiu IB: Analog decoding using a gradient-type neural network. IEEE Transactions on Neural Networks 1996, 7(4):1034–1038. 10.1109/72.508946

    Article  Google Scholar 

  4. Hamalainen A, Henriksson J: A recurrent neural decoder for convolutional codes. Proceedings of IEEE International Conference on Communications (ICC '99), June 1999, Vancouver, Canada 1305–1309.

    Google Scholar 

  5. Hamalainen A, Henriksson J: Convolutional decoding using recurrent neural networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN '99), July 1999, Washington, DC, USA 5: 3323–3327.

    Article  Google Scholar 

  6. Hamalainen A, Henriksson J: Novel use of channel information in a neural convolutional decoder. Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN '00), July 2000, Como, Italy 5: 337–342.

    Article  Google Scholar 

  7. Wang X-A, Wicker SB: Artificial neural net Viterbi decoder. IEEE Transactions on Communications 1996, 44(2):165–171. 10.1109/26.486609

    Article  Google Scholar 

  8. Buckley ME, Wicker SB: Neural network for predicting decoder error in turbo decoders. IEEE Communications Letters 1999, 3(5):145–147. 10.1109/4234.766850

    Article  Google Scholar 

  9. Rantala A, Vatunen S, Harinen T, Aberg M:A silicon efficient high speed rate convolutional decoder using recurrent neural networks Proceedings of 27th European Solid-State Circuits Conference (ESSCIRC '01), September 2001, Villach, Austria 452–455.

    Google Scholar 

  10. Berber SM, Secker PJ, Salcic Z:Theory and application of neural networks for rate convolutional decoders. Engineering Applications of Artificial Intelligence 2005, 18(8):931–949. 10.1016/j.engappai.2005.05.001

    Article  Google Scholar 

  11. Yu X, Dent D: Implementing neural networks in FPGAs. IEE Colloquium on Hardware Implementation of Neural Networks and Fuzzy Logic 1994, 61: 1/1–1/5.

    Google Scholar 

  12. Coric S, Latinovic I, Pavasovic A: A neural network FPGA implementation. Proceedings of the 5th Seminar on Neural Network Applications in Electrical Engineering (NEUREL '00), September 2000, Belgrade, Yugoslavia 117–120.

    Google Scholar 

  13. Bade SL, Hutchings BL: FPGA-based stochastic neural networks-implementation. Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, April 1994, Napa Valley, Calif, USA 189–198.

    Chapter  Google Scholar 

  14. Hammerstrom D: A VLSI architecture for high-performance, low-cost, on-chip learning. Proceedings of International Joint Conference on Neural Networks (IJCNN '90), June 1990, San Diego, Calif, USA 2: 537–544.

    Google Scholar 

  15. Maunder B, Salcic Z, Coghill G: High-level tool for the development of FPLD-based stochastic neural networks. Trends in Information Systems Engineering and Wireless Multimedia Communications Proceedings of the International Conference on Information, Communications and Signal Processing (ICICS '97), September 1997 2: 684–688.

    Article  Google Scholar 

  16. To W, Salcic Z, Nguang SK: Prototyping neuro-adaptive smart antenna for 3G wireless communications. EURASIP Journal on Applied Signal Processing 2005, 7: 1093–1109.

    MATH  Google Scholar 

  17. Blake JJ, Maguire LP, McGinnity TM, McDaid LJ: Using Xilinx FPGAs to implement neural networks and fuzzy systems. IEE Colloquium on Neural and Fuzzy Systems: Design, Hardware and Applications 1997, 133: 1/1–1/4.

    Google Scholar 

  18. Teich WG, Engelhart A, Schlecker W, Gessler R, Pfleiderer H-J: Towards an efficient hardware implementation of recurrent neural network based multiuser detection. Proceedings of IEEE 6th International Symposium on Spread Spectrum Techniques and Applications, September 2000, Parsippany, NJ, USA 2: 662–665.

    Article  Google Scholar 

  19. Abramson D, Smith K, Logothetis P, Duke D: FPGA based implementation of a Hopfield neural network for solving constraint satisfaction problems. Proceedings of Euromicro Conference (EUROMICRO '98), August 1998, Vesteras, Sweden 2: 688–693.

    Article  Google Scholar 

  20. Larsson P: Error correcting decoder implemented as a digital neural network with a new clocking scheme. Proceedings of the 36th Midwest Symposium on Circuits and Systems, August 1993, Detroit, Mich, USA 2: 1193–1195.

    Article  Google Scholar 

  21. The Mathworks Incorporated, https://doi.org/www.mathworks.com

  22. Altera Corporation, https://doi.org/www.altera.com

  23. Viterbi AJ: Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. IEEE Transactions on Information Theory 1967, 13(2):260–269.

    Article  Google Scholar 

  24. Alspector J, Gannett JW, Haber S, Parker MB, Chu R: A VLSI-efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks. IEEE Transactions on Circuits and Systems 1991, 38(1):109–123. 10.1109/31.101308

    Article  Google Scholar 

  25. Alspector J, Gannett JW, Haber S, Parker MB, Chu R: Generating multiple analog noise sources from a single linear feedback shift register with neural network applications. Proceedings of IEEE International Symposium on Circuits and Systems , May 1990, New Orleans, La, USA 2: 1058–1061.

    Article  Google Scholar 

  26. Secker P: The decoding of convolutional codes using artificial neural networks, M.S. thesis. The University of Auckland, Auckland, New Zealand; 2003.

    Google Scholar 

  27. Haykin SS: Communication Systems. John Wiley & Sons, New York, NY, USA; 2001.

    Google Scholar 

  28. Chu PP: Design techniques of FPGA based random number generator. Proceedings of Military and Aerospace Applications of Programmable Devices and Technologies Conference, September 1999, Laurel, Md, USA

    Google Scholar 

  29. IEEE Std 802.11a-1999 (Supplement to IEEE Std 802.11-1999), Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHZ Band

  30. Berber SM, Liu Y-C:Theoretical interpretation and investigation a rate convolutional decoder based on recurrent neural networks. Proceedings of The 4th International Conference on Information, Communications & Signal Processing (ICICS '03), December 2003, Singapore 5 pages, 2C3.5

    Google Scholar 

  31. Pandita B, Roy SK: Design and implementation of a Viterbi decoder using FPGAs. Proceedings of the IEEE International Conference on VLSI Design, October 1999, Austin, Tex, USA 611–614.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, the University of Auckland, 38 Princess Street, Auckland, 1020, New Zealand

    Zoran Salcic, Stevan Berber & Paul Secker

Authors
  1. Zoran Salcic
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Stevan Berber
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Paul Secker
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Zoran Salcic.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Salcic, Z., Berber, S. & Secker, P. FPGA Prototyping of RNN Decoder for Convolutional Codes. EURASIP J. Adv. Signal Process. 2006, 015640 (2006). https://doi.org/10.1155/ASP/2006/15640

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/ASP/2006/15640

Keywords