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FPGA Prototyping of RNN Decoder for Convolutional Codes
EURASIP Journal on Advances in Signal Processing volume 2006, Article number: 015640 (2006)
This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.
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Salcic, Z., Berber, S. & Secker, P. FPGA Prototyping of RNN Decoder for Convolutional Codes. EURASIP J. Adv. Signal Process. 2006, 015640 (2006). https://doi.org/10.1155/ASP/2006/15640
- Activation Function
- Quantum Information
- Communication Channel
- Design Specification
- Design Methodology