Skip to content


  • Research Article
  • Open Access

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

  • 1Email author,
  • 1, 2, 3,
  • 2 and
  • 1
EURASIP Journal on Advances in Signal Processing20062006:028636

  • Received: 3 October 2004
  • Accepted: 25 May 2005
  • Published:


We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.


  • Information Technology
  • Signal Processing
  • Digital Signal
  • Processing System
  • Quantum Information


Authors’ Affiliations

TIMA Laboratory, National Polytechnique Institute of Grenoble, 46 Avenue Félix Viallet, Grenoble Cedex 1, 38031, France
ST Microelectronics, 850 Rue Jean Monnet, Crolles Cedex, 38926, France
CIRAD, TA 40/01, avenue Agropolis Lavalette, Montpellier Cedex 5, 34398, France


  1. International Technology Roadmap for Semiconductors, 2003 Edition Report,
  2. Sangiovanni-Vincentelli A, Carloni L, De Bernardinis F, Sgroi M: Benefits and challenges for platform-based design. Proceedings of 41st IEEE Design Automation Conference (DAC '04), June 2004, San Diego, Claif, USA 409-414.View ArticleGoogle Scholar
  3. Martin G: Design methodologies for system level IP. Proceedings of IEEE Design, Automation and Test in Europe (DATE~'98), February 1998, Paris, France 286-289.View ArticleGoogle Scholar
  4. Gajski DD, Wu AC-H, Chaiyakul V, Mori S, Nukiyama T, Bricaud P: Essential issues for IP reuse. Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC '00), January 2000, Yokohama, Japan 37-42.Google Scholar
  5. Parhi KK: VLSI Digital Signal Processing Systems: Design and Implementation. John Wiley & Sons, New York, NY, USA; 1998.Google Scholar
  6. Celoxica : Handel-C Language Reference Manual. 2003. RM-1003-4.0,
  7. De Micheli G: Hardware synthesis from C/C++ models. Proceedings of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE '99), March 1999, Munich, Germany 382-383.Google Scholar
  8. Edwards SA: The challenges of hardware synthesis from C-like languages. Proceedings of IEEE Design, Automation and Test in Europe (DATE '05), March 2005, Munich, Germany 1: 66-67.View ArticleGoogle Scholar
  9. Gajski DD, Zhu J, Dömer R, Gerstlauser A, Zhoa S: Spec C: Specification Language and Methodology. Kluwer Academic, Boston, Mass, USA; 2000.View ArticleGoogle Scholar
  10. Ku DC, De Micheli G: HardwareC: A language for hardware design. In Tech. Rep. CSTL-TR-90-419. Computer Systems Laboratory, Stanford University, Stanford, Calif, USA; August 1990.Google Scholar
  11. SystemC Community,
  12. Xilinx System Generator v2.1 for Simulink Reference Guide, Xilinx, 2000Google Scholar
  13. Buck J, Ha S, Lee EA, Messerschmitt DG: Ptolemy: a framework for simulating and prototyping heterogeneous systems. International Journal of Computer Simulation 1994, 4(2):155-182.Google Scholar
  14. Balarin F, Chiodo M, Di Giusto P, et al.: Hardware-Software Co-Design of Embedded Systems: The POLIS Approach. Kluwer Academic, Boston, Mass, USA; 1997.View ArticleMATHGoogle Scholar
  15. Lauwereins R, Engels M, Ade M, Peperstraete JA: Grape-II: a system-level prototyping environment for DSP applications. IEEE Computer 1995 , 28(2):35-43. 10.1109/2.347998View ArticleGoogle Scholar
  16. Natarajan S, Levine B, Tan C, Newport D, Bouldin D: Automatic mapping of khoros-based applications to adaptive computing systems. Proceedings of Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD '99), Septemper 1999, Laurel, Md, USA 101-107.Google Scholar
  17. Spivey G, Bhattacharyya SS, Nakajima K: Logic foundry: rapid prototyping for FPGA-based DSP systems. EURASIP Journal on Applied Signal Processing 2003, 2003(6):565-579. 10.1155/S1110865703301039View ArticleMATHGoogle Scholar
  18. Banerjee P, Shenoy N, Choudhary A, et al.: MATCH: A MATLAB Compiler for Configurable Computing Systems. In Tech. Rep. CPDCTR-9908-013. Center for Parallel and Distributed Computing, Northwestern University, Evanston, Ill, USA; August 1999.Google Scholar
  19. Davis WR, Zhang N, Camera K, et al.: A design environment for high-throughput low-power dedicated signal processing systems. IEEE Journal of Solid-State Circuits 2002, 37(3):420-431. 10.1109/4.987095View ArticleGoogle Scholar
  20. Gupta RK, Zorian Y: Introducing core-based system design. IEEE Design and Test of Computers 1997, 14(4):15-25. 10.1109/54.632877View ArticleGoogle Scholar
  21. Lavagno L, Dey S, Gupta R: Specification, modeling and design tools for system-on-chip. Proceedings of 7th IEEE Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC '02), January 2002 , Bangalore, India 21-23.Google Scholar
  22. Cescirio W, Baghdadi A, Gauthier L, et al.: Component-based design approach for multicore SoCs. Proceedings of 39th IEEE Design Automation Conference (DAC '02), June 2002, New Orleans, La, USA 789-794.Google Scholar
  23. Kim B-W, Kyung C-M: Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002, 10(3):240-252.MathSciNetView ArticleGoogle Scholar
  24. Vachharajani M, Vachharajani N, Malik S, August DI: Facilitating reuse in hardware models with enhanced type inference. Proceedings of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '04), September 2004, Stockholm, Sweden 86-91.Google Scholar
  25. Passerone R, Rowson JA, Sangiovanni-Vincentelli A: Automatic synthesis of interfaces between incompatible protocols. Proceedings of 35th IEEE Design Automation Conference (DAC '98), June 1998, San Francico, Calif, USA 8-13.Google Scholar
  26. Choi H, Yi JH, Lee J-Y, Park I-C, Kyung C-M: Exploiting intellectual properties in ASIP designs for embedded DSP software. Proceedings of 36th IEEE Design Automation Conference (DAC '99), June 1999, New Orleans, La, USA 939-944.Google Scholar
  27. VSI Alliance,
  28. Tambour L: Efficient methodology for design and validation of complex DSP system-on-chip, Ph.D. thesis. Institut National Polytechnique de Grenoble (INPG), Grenoble, France; December 2003. Scholar
  29. Zergainoh NE, Popovici K, Jerraya AA, Urard P: Matlab based environment for designing DSP systems using IP blocks. Proceedings of 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '04), October 2004, Kanazawa, Japan 296-302.Google Scholar
  30. The MathWorks Incorporation,
  31. Zergainoh N, Tambour L, Michel H, Jerraya AA: Méthode de correction automatique de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP . Techniques et Sciences Informatiques 2005, 24(10):1227-1257. 10.3166/tsi.24.1227-1257View ArticleGoogle Scholar
  32. Gibbons A: Algorithmic Graph Theory. Cambridge University Press, Cambridge, UK; 1985.MATHGoogle Scholar
  33. Cesario WO, Nicolescu G, Gauthier L, Lyonnard D, Jerraya AA: Colif: A design representation for application-specific multiprocessor SOCs. IEEE Design and Test of Computers 2001, 18(5):8-20. 10.1109/54.953268View ArticleGoogle Scholar
  34. Synopsys Incorporation,


© Zergainoh et al. 2006