Open Access

A Fully Automated Environment for Verification of Virtual Prototypes

EURASIP Journal on Advances in Signal Processing20062006:032408

https://doi.org/10.1155/ASP/2006/32408

Received: 15 October 2004

Accepted: 25 May 2005

Published: 18 May 2006

Abstract

The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.

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Authors’ Affiliations

(1)
Institute of Communications and Radio Frequency Engineering, Vienna University of Technology

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Copyright

© P. Belanović et al. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.