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A Fully Automated Environment for Verification of Virtual Prototypes

Abstract

The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.

References

  1. 1.

    Moore GE: Cramming more components onto integrated circuits. Electronics Magazine 1965, 38(8):114–117.

    Google Scholar 

  2. 2.

    Subramanian R: Shannon vs Moore: driving the evolution of signal processing platforms in wireless communications. Proc. IEEE Workshop on Signal Processing Systems (SIPS '02), October 2002, San Diego, Calif, USA 2–2.

    Google Scholar 

  3. 3.

    International SEMATECH The International Technology Roadmap for Semiconductors, Austin, Tex, USA, 1999

  4. 4.

    Karsai G, Sztipanovits J, Ledeczi A, Bapty T: Model-integrated development of embedded software. Proc. IEEE 2003, 91(1):145–164. 10.1109/JPROC.2002.805824

    Article  Google Scholar 

  5. 5.

    Belanović P, Holzer M, Mičušík D, Rupp M: Design methodology of signal processing algorithms in wireless systems. Proc. International Conference on Computer, Communication and Control Technologies (CCCT '03), July–August 2003, Orlando, Fla, USA 288–291.

    Google Scholar 

  6. 6.

    Hemani A, Deb AK, Oberg J, Postula A, Lindqvist D, Fjellborg B: System level virtual prototyping of DSP SOCs using grammar based approach. Design Automation for Embedded Systems 2000, 5(3–4):295–311.

    Article  Google Scholar 

  7. 7.

    Valderrama CA, Changuel A, Jerraya AA: Virtual prototyping for modular and flexible hardware-software systems. Design Automation for Embedded Systems 1997, 2(3–4):267–282.

    Article  Google Scholar 

  8. 8.

    Voros NS, Sánchez L, Alonso A, Birbas AN, Birbas M, Jerraya A: Hardware-software co-design of complex embedded systems: an approach using efficient process models, multiple formalism specification and validation via co-simulation. Design Automation for Embedded Systems 2003, 8(1):5–49. 10.1023/A:1022388018837

    Article  Google Scholar 

  9. 9.

    Ernst R: Codesign of embedded systems: status and trends. IEEE Des. Test. Comput. 1998, 15(2):45–54. 10.1109/54.679207

    Article  Google Scholar 

  10. 10.

    Varma P, Bhatia S: A structured test re-use methodology for core-based system chips. Proc. IEEE International Test Conference (ITC '98), October 1998, Washington, DC, USA 294–302.

    Google Scholar 

  11. 11.

    Stöhr B, Simmons M, Geishauser J: FlexBench: reuse of verification IP to increase productivity. Proc. Design, Automation and Test in Europe Conference and Exposition (DATE '02), March 2002, Paris, France 1131–1131.

    Google Scholar 

  12. 12.

    Odin Technology : Axe Automated Testing Framework. 2004, https://doi.org/www.odin.co.uk/downloads/AxeFlyer.pdf

  13. 13.

    Belanović P, Holzer M, Knerr B, Rupp M, Sauzon G: Automatic generation of virtual prototypes. Proc. 15th International Workshop on Rapid System Prototyping (RSP '04), June 2004, Geneva, Switzerland 114–118.

    Google Scholar 

  14. 14.

    Belanović P, Knerr B, Holzer M, Sauzon G, Rupp M: A consistent design methodology for wireless embedded systems. EURASIP Journal on Applied Signal Processing Special issue on DSP enabled radio, 2005

    Google Scholar 

  15. 15.

    Knerr B, Holzer M, Rupp M: HW/SW partitioning using high level metrics. Proc. International Conference on Computer, Communication and Control Technologies (CCCT '04), August 2004, Austin, Tex, USA

    Google Scholar 

  16. 16.

    Bortfeld U, Mielenz C: White paper C++ System Simulation Interfaces. Infineon, Munich, Germany, July 2000

    Google Scholar 

  17. 17.

    The Open SystemC Initiative (OSCI), San Jose, Calif, USA, https://doi.org/www.systemc.org

  18. 18.

    CoWare Incorporation, "SoC Platform-Based Design Using ConvergenSC/SystemC," July 2002, https://doi.org/www.coware.com

  19. 19.

    Grötker T, Liao S, Martin G, Swan S: System Design with SystemC. Kluwer Academic, Boston, Mass, USA; 2002.

    Google Scholar 

  20. 20.

    StarCore DSP https://doi.org/www.starcore-dsp.com

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Correspondence to P Belanović.

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Belanović, P., Knerr, B., Holzer, M. et al. A Fully Automated Environment for Verification of Virtual Prototypes. EURASIP J. Adv. Signal Process. 2006, 032408 (2006). https://doi.org/10.1155/ASP/2006/32408

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Keywords

  • Wireless Communication
  • Quantum Information
  • Market Demand
  • Maximal Efficiency
  • Time Saving