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FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

Abstract

The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly on real-time implementation. Also, it focuses on a design methodology exploiting the modern technology of programmable logic and overcoming the limitations of commercial tools. The dedicated architecture based on a regular structure of processors and a special structure of memory exploiting FPGA architecture maximizes the processing rate. The proposed architecture was validated using synthesized data in UMTS communication scenarios. The performance goal is to maximize the number of users of different WCDMA data traffics. This dedicated architecture can be used as an intellectual property (IP) core processing an MUD function in the system-on-programmable-chip (SOPC) of UMTS systems. The targeted FPGA components are Virtex-II and Virtex-II Pro families of Xilinx.

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Correspondence to Quoc-Thai Ho.

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Ho, Q., Massicotte, D. & Dahmane, A. FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System. EURASIP J. Adv. Signal Process. 2006, 052919 (2006). https://doi.org/10.1155/ASP/2006/52919

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Keywords

  • Intellectual Property
  • Programmable Logic
  • Design Methodology
  • Performance Goal
  • Data Traffic