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FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System


The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly on real-time implementation. Also, it focuses on a design methodology exploiting the modern technology of programmable logic and overcoming the limitations of commercial tools. The dedicated architecture based on a regular structure of processors and a special structure of memory exploiting FPGA architecture maximizes the processing rate. The proposed architecture was validated using synthesized data in UMTS communication scenarios. The performance goal is to maximize the number of users of different WCDMA data traffics. This dedicated architecture can be used as an intellectual property (IP) core processing an MUD function in the system-on-programmable-chip (SOPC) of UMTS systems. The targeted FPGA components are Virtex-II and Virtex-II Pro families of Xilinx.


  1. 1.

    Chaudhury P, Mohr W, Onoe S: The 3GPP proposal for IMT-2000. IEEE Communications Magazine 1999, 37(12):72–81. 10.1109/35.809388

    Article  Google Scholar 

  2. 2.

    3rd Generation Partnership Project (3GPP) : Spreading and modulation (FDD). In Tech. Rep. TS 25.213 v4.1.0 (2001-06). 3GPP, Valbonne, France; 2001.

  3. 3.

    Verdú S: Multiuser Detection. Cambridge University Press, New York, NY, USA; 1998.

    Google Scholar 

  4. 4.

    Dahmane AO, Massicotte D: DS-CDMA receivers in Rayleigh fading multipath channels: direct vs. indirect methods. Proceedings of IASTED International Conference on Communications, Internet and Information Technology (CIIT '02), November 2002, St. Thomas, Virgin Islands, USA

    Google Scholar 

  5. 5.

    Dahmane AO, Massicotte D: Wideband CDMA receivers for 3G wireless communications: algorithm and implementation study. Proceedings of IASTED International Conference on Wireless and Optical Communications (WOC '02), July 2002, Banff, Alberta, Canada

    Google Scholar 

  6. 6.

    Moshavi S: Multi-user detection for DS-CDMA communications. IEEE Communications Magazine 1996, 34(10):124–136. 10.1109/35.544334

    Article  Google Scholar 

  7. 7.

    Rajagopal S, Bhashyam S, Cavallaro JR, Aazhang B: Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers. IEEE Transaction on Wireless Communications 2002, 1(3):468–479. 10.1109/TWC.2002.800545

    Article  Google Scholar 

  8. 8.

    Leung O, Tsui C-Y, Cheng RS: VLSI implementation of rake receiver for IS-95 CDMA testbed using FPGA. Proceedings of IEEE Asia and South Pacific on Design Automation Conference (ASP-DAC '00), January 2000, Yokohama, Japan 3–4.

    Google Scholar 

  9. 9.

    Xu G, Rajagopal S, Cavallaro J, Aazhang B: VLSI implementation of the multistage detector for next generation wideband CDMA receivers. The Journal of VLSI Signal Processing 2002, 30(1–3):21–33.

    Article  Google Scholar 

  10. 10.

    Guo Y, Xu G, McCain D, Cavallaro JR: Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer. Proceedings of 14th IEEE International Workshop on Rapid Systems Prototyping (RSP '03), June 2003, San Diego, Calif, USA 179–185.

    Google Scholar 

  11. 11.

    Schlecker W, Engelhart A, Teich WG, Pfleiderer H-J: FPGA hardware implementation of an iterative multiuser detection scheme. Proceedings of 10th Aachen Symposium on Signal Theory (ASST '01), September 2001, Aachen,Germany 293–298.

    Google Scholar 

  12. 12.

    Jones BA, Cavallaro JR: A rapid prototyping environment for wireless communication embedded systems. EURASIP Journal on Applied Signal Processing 2003, 2003(6):603–614. Special issue on rapid prototyping of DSP systems 10.1155/S111086570330304X

    MATH  Google Scholar 

  13. 13.

    Massicotte D, Dahmane AO: Cascade filter receiver for DS-CDMA communication systems. International Application Published Under the Patent Cooperation Treaty (PCT), May 2004, WO2004/040789

  14. 14.

    Ho Q-T, Massicotte D: FPGA implementation of adaptive multiuser detector for DS-CDMA systems. Proceedings of 14th International Conference on Field Programmable Logic and Application (FPL '04), August–September 2004, Leuven, Belgium 959–964.

    Google Scholar 

  15. 15.

    Ho Q-T, Massicotte D: A low complexity adaptive multiuser detector and FPGA implementation for wireless DS-WCDMA communication systems. Proceedings of Global Signal Processing Expo and Conference (GSPx '04), September 2004, Santa Clara, Calif, USA

    Google Scholar 

  16. 16.

    The International Telecommunication Union (ITU) Geneva, Switzerland, available at:

  17. 17.

    Xilinx San Jose, Calif, USA, available at:

  18. 18.

    De Micheli G: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, NY, USA; 1994.

    Google Scholar 

  19. 19.

    Nash SG, Sofer A: Linear and Nonlinear Programming. McGraw-Hill, New York, NY, USA; 1996.

    Google Scholar 

  20. 20.

    Rajagopal S, Rixner S, Cavallaro JR: A programmable baseband processor design for software defined radios. Proceedings of 45th IEEE Midwest Symposium on Circuits and Systems (MWSCAS '02), August 2002, Tulsa, Okla, USA 3: 413–416.

    Google Scholar 

  21. 21.

    Shi C, Hwang J, McMillan S, Root A, Singh V: A system level resource estimation tool for FPGAs. Proceedings of 14th International Conference on Field Programmable Logic and Application (FPL '04), August–September 2004, Leuven, Belgium 424–433.

    Google Scholar 

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Correspondence to Quoc-Thai Ho.

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Ho, Q., Massicotte, D. & Dahmane, A. FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System. EURASIP J. Adv. Signal Process. 2006, 052919 (2006).

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  • Intellectual Property
  • Programmable Logic
  • Design Methodology
  • Performance Goal
  • Data Traffic