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An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

Abstract

We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

References

  1. 1.

    Gesbert D, Shafi M, Shiu D, Smith PJ, Naguib A: From theory to practice: an overview of MIMO space-time coded wireless systems. IEEE Journal on Selected Areas in Communications 2003, 21(3):281–302. 10.1109/JSAC.2003.809458

  2. 2.

    Golden GD, Foschini CJ, Valenzuela RA, Wolniansky PW: Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture. Electronics Letters 1999, 35(1):14–16. 10.1049/el:19990058

  3. 3.

    Foschini GJ: Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas. Bell Labs Technical Journal 1996, 1(2):41–59.

  4. 4.

    Holma H, Toskala A: Wideband CDMA for UMTS. John Wiley & Sons, New York, NY, USA; 2000.

  5. 5.

    Wiesel A, García L, Vidal J, Pagès A, Fonollosa JR: Turbo linear dispersion space time coding for MIMO HSDPA systems. Proceedings of 12th IST Summit on Mobile and Wireless Communications, June 2003, Aveiro, Portugal

  6. 6.

    Hooli K, Juntti M, Heikkilä MJ, Komulainen P, Latva-aho M, Lilleberg J: Chip-level channel equalization in WCDMA downlink. EURASIP Journal on Applied Signal Processing 2002, 2002(8):757–770. 10.1155/S1110865702000914

  7. 7.

    Das S, Sengupta C, Cavallaro JR: Hardware design issues for a mobile unit for next-generation CDMA systems. Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, July 1998, San Diego, Calif, USA, Proceedings of SPIE 3461: 476–487.

  8. 8.

    Scharf LL: Statistical Signal Processing: Detection, Estimation, and Time Series Analysis. Addison-Wesley, New York, NY, USA; 1990.

  9. 9.

    Kailath T, Chun J: Generalized displacement structure for block-Toeplitz, Toeplitz-block, and Toeplitz-derived matrices. SIAM Journal on Matrix Analysis and Applications 1994, 15(1):114–128. 10.1137/S0895479889169042

  10. 10.

    Chandrasekarnan S, Sayed AH: Stablizing the generalized schur algorithm. SIAM Journal on Matrix Analysis and Applications 1996, 17(4):950–983. 10.1137/S0895479895287419

  11. 11.

    Heikkila MJ, Ruotsalainen K, Lilleberg J: Space-time equalization using conjugate-gradient algorithm in WCDMA downlink. Proceedings of 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC '02), September 2002, Lisbon, Portugal 2: 673–677.

  12. 12.

    Jevic FR, Cavallaro JR, de Baynast A: ASIP architecture implementation of channel equalization algorithms for MIMO systems in WCDMA downlink. Proceedings of 60th IEEE Vehicular Technology Conference (VTC '04), September 2004, Los Angeles, Calif, USA 3: 1735–1739.

  13. 13.

    Guo Y, Xu G, McCain D, Cavallaro JR: Rapid scheduling of efficient VLSI architectures for next-generation HSDPA wireless system using Precision C synthesizer. Proceedings of 14th IEEE International Workshop on Rapid Systems Prototyping (RSP '03), June 2003, San Diego, Calif, USA 179–185.

  14. 14.

    https://doi.org/www.nokia.com/nokia/0,,53713,00.html

  15. 15.

    Wrolstad J: Bell Labs BLASTs New High-Speed Wireless Chips. Wireless NewsFactor, Los Angeles, Calif, USA; 2002.

  16. 16.

    Guo Z, Edman F, Nilsson P, Ovall V: On VLSI implementations of MIMO detectors for future wireless communications. Proceedings of 1st IST-MAGNET Workshop, November 2004, Shanghai, China

  17. 17.

    Guo Y, McCain D, Zhang J, Cavallaro JR: Scalable FPGA architectures for LMMSE-based SIMO chip equalizer in HSDPA downlink. Proceedings of 37th Asilomar Conference on Signals, Systems and Computers, November 2003, Monterey, Calif, USA 2: 2171–2175.

  18. 18.

    Evans A, Silburt A, Vrckovnik G, et al.: Functional verification of large ASICs. Proceedings of 35th ACM/IEEE Design Automation Conference (DAC '98), June 1998, San Francisco, Calif, USA 650–655.

  19. 19.

    Bellows P, Hutchings B: JHDL-An HDL for reconfigurable systems. In Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, April 1998, Napa Valley, Calif, USA. IEEE Computer Society Press; 175–184.

  20. 20.

    Guo Y, Zhang J, McCain D, Cavallaro JR: Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study. Proceedings of IEEE Global Telecommunications Conference (GLOBECOM~'04), November 2004, Dallas, Tex, USA 4: 2513–2519.

  21. 21.

    Rajagopal S, Jones BA, Cavallaro JR: Task partitioning wireless base-station receiver algorithms on multiple DSPs and FPGAs. Proceedings of International Conference on Signal Processing Applications and Technology (ICSPAT '00), October 2000, Dallas, Tex, USA

  22. 22.

    Horn RA, Johnson CR: Matrix Analysis. Cambridge University Press, New York, NY, USA; 1985.

  23. 23.

    Kermoal JP, Schumacher L, Pedersen KI, Mogensen PE, Frederiksen F: A stochastic MIMO radio channel model with experimental validation. IEEE Journal on Selected Areas in Communications 2002, 20(6):1211–1226. 10.1109/JSAC.2002.801223

  24. 24.

    Nguyen H, Zhang J, Raghothaman B: A Kalman-filter approach to equalization of CDMA downlink channels. EURASIP Journal on Applied Signal Processing 2005, 2005(5):611–625. 10.1155/ASP.2005.611

  25. 25.

    Burg A, Rupp M, Guillaud M, et al.: FPGA implementation of a MIMO receiver front-end for the UMTS downlink. Proceedings of International Zurich Seminar on Broadband Communications (IZS '02), February 2002, Zurich, Switzerland 8-1–8-6.

  26. 26.

    Mentor Graphics : Catapult C Manual and C/C++ style guide. 2004.

  27. 27.

    Knippin U: Early design evaluation in hardware and system prototyping for concurrent hardware/software validation in one environment. Proceedings of 13th IEEE International Workshop on Rapid System Prototyping (RSP '02), July 2002, Darmstadt, Germany

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Correspondence to Yuanbin Guo.

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Guo, Y., Zhang, J., McCain, D. et al. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture. EURASIP J. Adv. Signal Process. 2006, 057134 (2006). https://doi.org/10.1155/ASP/2006/57134

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Keywords

  • Information Technology
  • Quantum Information
  • Design Space
  • Matrix Inverse
  • Complexity Reduction