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Efficient and Secure Fingerprint Verification for Embedded Devices

Abstract

This paper describes a secure and memory-efficient embedded fingerprint verification system. It shows how a fingerprint verification module originally developed to run on a workstation can be transformed and optimized in a systematic way to run real-time on an embedded device with limited memory and computation power. A complete fingerprint recognition module is a complex application that requires in the order of 1000 M unoptimized floating-point instruction cycles. The goal is to run both the minutiae extraction and the matching engines on a small embedded processor, in our case a 50 MHz LEON-2 softcore. It does require optimization and acceleration techniques at each design step. In order to speed up the fingerprint signal processing phase, we propose acceleration techniques at the algorithm level, at the software level to reduce the execution cycle number, and at the hardware level to distribute the system work load. Thirdly, a memory trace map-based memory reduction strategy is used for lowering the system memory requirement. Lastly, at the hardware level, it requires the development of specialized coprocessors. As results of these optimizations, we achieve a 65% reduction on the execution time and a 67% reduction on the memory storage requirement for the minutiae extraction process, compared against the reference implementation. The complete operation, that is, fingerprint capture, feature extraction, and matching, can be done in real-time of less than 4 seconds

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Correspondence to Shenglin Yang.

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Yang, S., Sakiyama, K. & Verbauwhede, I. Efficient and Secure Fingerprint Verification for Embedded Devices. EURASIP J. Adv. Signal Process. 2006, 058263 (2006). https://doi.org/10.1155/ASP/2006/58263

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Keywords

  • Acceleration Technique
  • Embed Processor
  • Minutia Extraction
  • Execution Cycle
  • Hardware Level