Open Access

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

  • Chul Kim1,
  • Alex Rassau1,
  • Stefan Lachowicz1,
  • Mike Myung-Ok Lee2 and
  • Kamran Eshraghian3
EURASIP Journal on Advances in Signal Processing20062006:075032

https://doi.org/10.1155/ASP/2006/75032

Received: 1 October 2004

Accepted: 25 May 2005

Published: 20 February 2006

Abstract

This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch) through an indium bump interconnection array (IBIA). The configurable array processor (CAP) is an array of heterogeneous processing elements (PEs), while the intelligent configurable switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA) controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

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Authors’ Affiliations

(1)
Centre for Very High Speed Microelectronic Systems, Edith Cowan University
(2)
School of Information and Communication Engineering, Dongshin University
(3)
Eshraghian Laboratories Pty Ltd, Technology Park

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Copyright

© Kim et al. 2006