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  • Research Article
  • Open Access

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

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  • 1,
  • 1,
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EURASIP Journal on Advances in Signal Processing20062006:075032

  • Received: 1 October 2004
  • Accepted: 25 May 2005
  • Published:


This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch) through an indium bump interconnection array (IBIA). The configurable array processor (CAP) is an array of heterogeneous processing elements (PEs), while the intelligent configurable switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA) controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.


  • Vertical Integration
  • Data Frame
  • Hardware Specification
  • Direct Memory Access
  • Heterogeneous Processing

Authors’ Affiliations

Centre for Very High Speed Microelectronic Systems, Edith Cowan University, Joondalup, WA, 6027, Australia
School of Information and Communication Engineering, Dongshin University, Naju, Chonnam, 520714, Korea
Eshraghian Laboratories Pty Ltd, Technology Park, Bentley, WA, 6102, Australia


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© Kim et al. 2006