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Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding

Abstract

This paper presents an iteration space partitioning scheme to reduce the CPU idle time due to the long memory access latency. We take into consideration both the data accesses of intermediate and initial data. An algorithm is proposed to find the largest overlap for initial data to reduce the entire memory traffic. In order to efficiently hide the memory latency, another algorithm is developed to balance the ALU and memory schedules. The experiments on DSP benchmarks show that the algorithms significantly outperform the known existing methods.

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Correspondence to Zhong Wang.

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Wang, Z., Sha, E.HM. & Wang, Y. Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding. EURASIP J. Adv. Signal Process. 2002, 391670 (2002). https://doi.org/10.1155/S1110865702205041

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Keywords

  • loop pipelining
  • initial data
  • maximal overlap
  • balanced partition scheduling