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Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications

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Abstract

This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.

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Correspondence to Kimmo Kuusilinna.

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Kuusilinna, K., Chang, C., Ammer, M.J. et al. Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications. EURASIP J. Adv. Signal Process. 2003, 205943 (2003) doi:10.1155/S1110865703212154

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Keywords

  • rapid prototyping
  • FPGA
  • hardware emulation
  • low power
  • design flow