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  • Research Article
  • Open Access

Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications

  • 1, 2Email author,
  • 2,
  • 2,
  • 2 and
  • 2
EURASIP Journal on Advances in Signal Processing20032003:205943

https://doi.org/10.1155/S1110865703212154

  • Received: 28 February 2002
  • Published:

Abstract

This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.

Keywords

  • rapid prototyping
  • FPGA
  • hardware emulation
  • low power
  • design flow

Authors’ Affiliations

(1)
Tampere University of Technology, Korkeakoulunkatu 1, P.O. Box. 553, Tampere, FIN-33101, Finland
(2)
Berkeley, Berkeley Wireless Research Center, University of California, 2108 Allston Way, Berkeley, CA 94704, USA

Copyright

© Copyright © 2003 Hindawi Publishing Corporation 2003

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