Open Access

Low-Power Embedded DSP Core for Communication Systems

  • Ya-Lan Tsao1Email author,
  • Wei-Hao Chen1,
  • Ming Hsuan Tan1,
  • Maw-Ching Lin1 and
  • Shyh-Jye Jou1
EURASIP Journal on Advances in Signal Processing20032003:232360

https://doi.org/10.1155/S1110865703309059

Received: 2 February 2003

Published: 24 December 2003

Abstract

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m) and 140 MHz (0.25 m).

Keywords

digital signal processor embedded system dual MAC subword multiplier

Authors’ Affiliations

(1)
Department of Electrical Engineering, National Central University

Copyright

© Copyright © 2003 Hindawi Publishing Corporation 2003