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Interleaved Convolutional Code and Its Viterbi Decoder Architecture

Abstract

We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with delays, interleaved Viterbi decoder is obtained where is the interleaving degree. The decoding speed of this decoder architecture is as fast as the operating clock speed. The latency of proposed interleaved Viterbi decoder is "decoding depth (DD) interleaving degree," which increases linearly with the interleaving degree.

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Correspondence to Jun Jin Kong.

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Kong, J.J., Parhi, K.K. Interleaved Convolutional Code and Its Viterbi Decoder Architecture. EURASIP J. Adv. Signal Process. 2003, 417892 (2003). https://doi.org/10.1155/S1110865703309126

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Keywords

  • interleaved convolutional code
  • interleaved Viterbi decoder
  • burst-error correction
  • random-error correction
  • interleaving