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  • Research Article
  • Open Access

Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

EURASIP Journal on Advances in Signal Processing20032003:253436

  • Received: 31 January 2003
  • Published:


This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25 m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.


  • Reed-Solomon
  • application-specific DSP
  • GF multiplier
  • broadband communication
  • VLSI architecture

Authors’ Affiliations

School of Electrical and Computer Engineering, Ajou University, San 5, Wonchun-Dong, Paldal-Gu, Suwon, 442-749, Korea
Computer System Department, Electronics and Telecommunications Research Institute, 161 Gajeong-Dong, Yuseong-Gu, Taejon, 305-350, Korea


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