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Open Access

A Novel High-Speed Configurable Viterbi Decoder for Broadband Access

EURASIP Journal on Advances in Signal Processing20032003:865460

Received: 31 January 2003

Published: 24 December 2003


A novel design and implementation of an online reconfigurable Viterbi decoder is proposed, based on an area-efficient add-compare-select (ACS) architecture, in which the constraint length and traceback depth can be dynamically reconfigured. A design-space exploration to trade off decoding capability, area, and decoding speed has been performed, from which the maximum level of pipelining against the number of ACS units to be used has been determined while maintaining an in-place path metric updating. An example design with constraint lengths from 7 to 10 and a 5-level ACS pipelining has been successfully implemented on a Xilinx Virtex FPGA device. FPGA implementation results, in terms of decoding speed, resource usage, and BER, have been obtained using a tailored testbench. These confirmed the functionality and the expected higher speeds and lower resources.


pipeliningconfigurableACSarea-efficient architecturedesign-space explorationschedule

Authors’ Affiliations

Department of Electronic and Electrical Engineering, The University of Sheffield, Sheffield, UK


© Copyright © 2003 Hindawi Publishing Corporation 2003