EURASIP Journal on Advances in Signal Processing

Table 1 CSD representation of filter coefficients.

From: Efficient implementation of 90° phase shifter in FPGA

Coefficient	Value	CSD representation
h(0) = -h(26)	-0.00774850	-2^-7 + 2^-12
h(1) = -h(25)	0	0
h(2) = -h(24)	-0.015821939	-2^-6
h(3) = -h(23)	0	0
h(4) = -h(22)	-0.031142897	-2^-5-2^-12
h(5) = -h(21)	0	0
h(6) = -h(20)	-0.056424022	-2^-4 + 2^-7-2^-9
h(7) = -h(19)	0	0
h(8) = -h(18)	-0.100431833	-2^-3 + 2^-5-2^-7 + 2^-10 + 2^-12
h(9) = -h(17)	0	0
h(10) = -h(16)	-0.195105144	-2^-2 + 2^-4-2^-7 + 2^-12
h(11) = -h(15)	0	0
h(12) = -h(14)	-0.630749788	-2^-1-2^-3-2^-7 + 2^-9 + 2^-12
h(13)	0	0

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