Table 2 Design summary reported by Xilinx ISE for first order design of the proposed method
From: A sigma–delta analog to digital converter based on iterative algorithm
Logic utilization | Used | Available | Utilization (%) |
|---|---|---|---|
Total number slice registers | 204 | 178,176 | 1 |
Number used as flip flops | 199 | N.A. | N.A. |
Number used as latches | 5 | N.A. | N.A. |
Number of four input LUTs | 761 | 178,176 | 1 |
Number of occupied slices | 459 | 89,088 | 1 |
Number of slices containing only related logic | 459 | 459 | 100 |
Number of slices containing unrelated logic | 0 | 459 | 0 |
Total number of four input LUTs | 764 | 178,176 | 1 |
Number used as logic | 761 | N.A. | N.A |
Number used as a route-thru | 3 | N.A. | N.A. |
Number of bonded IOBs | 143 | 960 | 14 |
IOB flip flops | 5 | N.A. | N.A. |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3 |