Table 5 The resources utilization for the three proposed architectures on the Xilinx Virtex 5 FPGA xc5vlx50t-3-ff1136
From: Proposed hardware architectures of particle filter for object tracking
Device utilization summary | ||||
|---|---|---|---|---|
Resource | Single PE with sequential resampling | Single PE with parallel resampling | Distributed PF 8 PE | FPGA available resources |
Slice registers | 891 | 967 | 9049 | 28800 |
Slice LUTs | 1203 | 4430 | 15017 | 28800 |
Fully used Bit Slices | 364 | 746 | 2517 | 21549 |
Bonded IOBs | 28 | 28 | 148 | 480 |
Block RAM/FIFO | 1 | 1 | 4 | 60 |
BUFG/BYFGCTRLs | 2 | 2 | 2 | 32 |
DSP48Es | 5 | 48 | 17 | 48 |