Table 2 Gray mapping for 3-bit/cell flash memories
From: Verify level control criteria for multi-level cell flash memories and their applications
State | S 0 | S 1 | S 2 | S 3 | S 4 | S 5 | S 6 | S 7 |
|---|---|---|---|---|---|---|---|---|
page 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
page 2 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
page 3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |