Table 1 LDPC decoder design results at 65-nm technology node
From: Reducing latency overhead caused by using LDPC codes in NAND flash memory
Silicon area (mm2) | Throughput | |||||
|---|---|---|---|---|---|---|
Computation | Register array | SRAM | Others | Total | ||
Soft-decision decoder | 0.40 | 0.26 | 1.96 | 0.19 | 2.81 | 2.1 Gbps |
Hard-decision decoder | 0 | 0.06 | 0.38 | 0.26 | 0.70 | @ 300 MHz |