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Table 8 Hardware overhead of ECC scheme for STT-RAM

From: Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

   Energy (pJ) Latency (ns) Area Extra storage rate (%)
512 bits BCH(542,512) 42.4 85.6 2840 5.5
1024 bits BCH(1057,1024) 100.4 192.5 3525 3.1
2048 bits BCH(2084,2048) 272.7 459.7 3838 1.7