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Table 9 Hardware overhead of ECC scheme for MLC-PRAM

From: Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

   Energy (pJ) Latency (ns) Area Extra storage rate (%)
512 bits BCH(552,512) 56.3 86.5 3386 7
1024 bits BCH(1079,1024) 187.8 194.5 5732 5.9
2048 bits BCH(2120,2048) 585.5 463.7 6717 1.7
  Flexible ECC 98.6 179.4 2051 16.4