Table 3 FPGA resource requirements to implementation proposed algorithm result
From: Design and implementation of a real time and train less eye state recognition system
Logic utilization | Used | Available | Utilization (%) |
|---|---|---|---|
Number of slices | 1136 | 23872 | 4 |
Number of slice flip flops | 836 | 47744 | 1 |
Number of 4 input LUTs | 2071 | 47744 | 4 |
Number of BRAMs | 1 | 126 | 0 |