TY - JOUR AU - González, Diego AU - Botella, Guillermo AU - García, Carlos AU - Prieto, Manuel AU - Tirado, Francisco PY - 2013 DA - 2013/06/16 TI - Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor JO - EURASIP Journal on Advances in Signal Processing SP - 118 VL - 2013 IS - 1 AB - This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor. SN - 1687-6180 UR - https://doi.org/10.1186/1687-6180-2013-118 DO - 10.1186/1687-6180-2013-118 ID - González2013 ER -