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Table 6 Memory system design configuration

From: Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

Design

Memories

Processor reset vector

Processor exception vector

Stack

Heap

Read/write data (.rwdata)

Read only data (.rodata)

Program (.text)

1

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

2

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

On-Chip

3

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

On-Chip

On-Chip

4

SDRAM

SDRAM

SDRAM

SDRAM

On-Chip

SDRAM

SDRAM

5

SDRAM

SDRAM

SDRAM

SDRAM

On-Chip

On-Chip

SDRAM

6

SDRAM

SDRAM

On-Chip

SDRAM

SDRAM

SDRAM

SDRAM

7

SDRAM

SDRAM

On-Chip

SDRAM

On-Chip

SDRAM

SDRAM

8

SDRAM

SDRAM

On-Chip

SDRAM

On-Chip

On-Chip

SDRAM

9

On-chip

On-chip

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

10

On-chip

On-chip

SDRAM

SDRAM

SDRAM

On-chip

SDRAM

11

On-chip

On-chip

SDRAM

SDRAM

On-chip

SDRAM

SDRAM

12

On-chip

On-chip

SDRAM

SDRAM

On-chip

On-Chip

SDRAM

13

On-chip

On-chip

On-chip

SDRAM

SDRAM

SDRAM

SDRAM

14

On-chip

On-chip

On-chip

SDRAM

SDRAM

On-chip

SDRAM

15

On-chip

On-chip

On-chip

SDRAM

On-chip

SDRAM

SDRAM

16

On-chip

On-chip

On-chip

SDRAM

On-chip

On-chip

SDRAM