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Table 7 FPGA used resources

From: Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

FPGA resources
Logic cells Dedicated logic registers I/O registers Memory bits M4Ks DSP elements DSP 9 × 9 DSP 18 × 18 Pins Virtual pins LUT-only LCs Register-only LCs LUT/register LCs
2202(1) 1050(0) 52(52) 306,176 78 0 0 0 56 0 1,152(1) 148(0) 902(0)
2198(1) 1050(0) 52(52) 306,176 78 0 0 0 56 0 1,148(1) 148(0) 902(0)
2352(1) 1051(0) 52(52) 306,176 78 0 0 0 56 0 1,301(1) 148(0) 903(0)
2348(1) 1051(0) 52(52) 306,176 78 0 0 0 56 0 1,297(1) 146(0) 905(0)
3152(1) 1755(0) 52(52) 341,632 87 4 0 2 56 0 1,397(1) 228(0) 1,527(0)
3150(1) 1755(0) 52(52) 341,632 87 4 0 2 56 0 1,395(1) 225(0) 1,530(0)
3284(1) 1756(0) 52(52) 341,632 87 4 0 2 56 0 1,528(1) 223(0) 1,533(0)
3285(1) 1756(0) 52(52) 341,632 87 4 0 2 56 0 1,529(1) 223(0) 1,533(0)
3868(1) 2175(0) 52(52) 377,088 98 4 0 2 56 0 1,693(1) 363(0) 1,812(0)
3858(1) 2175(0) 52(52) 377,088 98 4 0 2 56 0 1,683(1) 360(0) 1,815(0)
3973(1) 2178(0) 52(52) 377,088 98 4 0 2 56 0 1,795(1) 360(0) 1,818(0)
3968(1) 2178(0) 52(52) 377,088 98 4 0 2 56 0 1,790(1) 360(0) 1,818(0)