Table 2 The list of the utilized Xilinx FPGAs for our implemented DL MU-MIMO transceiver
| Â | Model | Unit | Application | Occupied slices (%) |
|---|---|---|---|---|
AP | Virtex5 SX95T | 1 | Weight computation | 90 |
Virtex5 SX95T | 3 | Transmitter signal processing | 95 | |
Virtex5 FX70T | 1 | Controlling four Virtex5 SX95T, CSI acquisition | 67 | |
Virtex4 SX55 | 1 | Receiver signal processing | 83 | |
Six users | Virtex5 SX95T | 2 | Transmitter signal processing | 56 |
Virtex4 SX55 | 6 | Receiver signal processing | 90 |