Table 4 Implementation results of the devised PEs in a Xilinx Virtex-7 FPGA
From: Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
Processing structure | Registers | LUTs | Maximum frequency |
|---|---|---|---|
[MHz] | |||
PE for AVC | 67 | 124 | 371.5 |
PE for AVS | 66 | 111 | 395.3 |
PE for VC-1 | 65 | 160 | 302.0 |
PE for HEVC | 79 | 253 | 289.3 |
Multi-standard PE | 80 | 299 | 285.3 |