Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

EURASIP Journal on Advances in Signal Processing

Table 5 Implementation results of the proof-of-concept MST core in a Xilinx Virtex-7 FPGA

Processing structure	Registers	LUTs	Maximum frequency
			[MHz]
MST core	7,309	21,568	279.4
Input buffer	1,681	1,265	388.7
Array with 8×8 PEs	5,332	18,624	284.1
PE	80	299	285.3
Transposition switch	1,362	2,161	417.4
Control unit	97	77	573.1