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Table 4 Chip implementation details

From: Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Technology 45-nm CMOS
Voltage 1.08 V
Process 1P6M
PVT conditions Typical
Word length 64 bits
FFT size 32 to 2,048
Internal RAM 1.25 KB
Maximum frequency 100 MHz
Core area 0.973 mm2
Cell count 307,201
Leakage power 0.034 mW
Total power 68.17 mW
Energy per FFT 14 nJ for 2,048 points