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Table 7 Comparison of design features and performance of various FFT processors

From: Low power reconfigurable FP-FFT core with an array of folded DA butterflies

 

This work

[Kai-Jiun]

[Chia]

[Song]

[Chu yu]

[Manish]

Technology

45 nm

90 nm

65 nm

180 nm

180 nm

180 nm

Voltage (Vdd)

1.08 V

1 V

0.45 V

1.8 V

1.8 V

1.8 V

Architecture/algorithm

Array-based, DFPABF/radix-2

MDC, 4-stream, Radix-4/8

Mixed radix MDF

Flexible radix, MDF multiple stream

Pipelined, SDF

R2SDF

FFT size/modes

Variable 64 to 2,048

Variable 128 to 2,048

Variable 128 to 2,048

128/256/512/1024

Fixed 64

Variable 128 to 2,048

1-4 streams

Maximum frequency

100 MHz

40 MHz

20 MHz

300 MHz

20 MHz

40 MHz

Word length

64 bits

16 bits (input)

24

20

16

32

Memory

3.25 KB internal memory (RAM + ROM)

Dual port SRAM (10,224 × 16 bits)

48 KB of register file

Mixed SRAM

DL buffers

FIFO of varying sizes

Core area

0.973 mm2

3.1 mm2

1.375 mm2

3.2 mm2

0.88 mm2

4.52 mm2

Power consumption

68 mW

63.72 mW

4.05

507 mW at 512 points

9.79 mW

55.64 mW

Normalized area

0.475

1.51

0.858

1.25

3.45

0.275

Normalized power

0.332 μw

3.62 μw

1.51 μw

3.8 μw

11 μw

0.489 μw