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EURASIP Journal on Advances in Signal Processing

Table 2 Proposed algorithm’s performance in terms of complexity reduction and power consumption for different decimation factors D

From: Approximate computing for complexity reduction in timing synchronization

D factor

Algorithm complexity

Normalized working

Normalized

Normalized estimated

 

reduction

frequency

Vdd

power

2

1/2

0.50

0.65

0.22

3

1/3

0.67

0.75

0.36

4

1/4

0.75

0.8

0.44

5

1/5

0.80

0.85

0.55

  1. The values of working frequency, supply voltage (Vdd) and estimated power consumptions were normalized respective to their maximums.
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