Table 3 Comparison of hardware resource consumption with the reported architectures on Xilinx Virtex-7 XC7V585T-2LFFG1761C device
From: Area and power efficient DCT architecture for image compression
Transform | LUTs | Cell usage | Delay (ns) |
|---|---|---|---|
SDCT[17] | 272 | 274 | 5.113 |
Bouguezel et al.[19] | 267 | 269 | 4.149 |
Bouguezel et al.[21] | 204 | 206 | 5.716 |
Bouguezel et al.[22] | 271 | 273 | 5.153 |
Bouguezel et al.[23] (a = 1) | 204 | 205 | 5.593 |
Senapati et al.[26] | 186 | 189 | 5.914 |
Cintra and Bayer[24] | 226 | 228 | 5.171 |
Bayer and Cintra[27] | 153 | 155 | 4.580 |
Transform in[29] | 167 | 168 | 6.738 |
Transform in[30] | 156 | 157 | 5.924 |
Proposed transform | 132 | 134 | 3.247 |