Table 5 Comparison chart of existing TP multiplier, proposed TP multiplier and non-TP
From: An optimised twin precision multiplier for ASIC environment
Non-TPM | Twin 2009 [ 2 ] | Proposed twin | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Bit width | 8 | 16 | 32 | 64 | 128 | 8 | 16 | 32 | 64 | 128 | 8 | 16 | 32 | 64 | 128 |
Mux | - | - | - | - | - | 11 | 19 | 35 | 67 | 131 | 7 | 11 | 19 | 35 | 67 |
Area (μm2) (cells) | 398 | 1,385 | 5,247 | 19,706 | 74,390 | 444 | 1,603 | 6,412 | 25,780 | 103,320 | 412 | 1,458 | 216,552 | 90,836 | |
Delay (ps) | 359 | 692.27 | 1,273.8 | 2,553.5 | 5,481.65 | 394.6 | 818.5 | 1,627.4 | 3,453.8 | 7,865.3 | 378.2 | 7438 | 1,415.4 | 2,935.05 | 6,449 |
Power (nW) | 13,051.8 | 362,256.4 | 731,984.4 | 1,548,441.2 | 3,478,721.9 | 12,198 | 320,581 | 609,987 | 1,200,342 | 2,576,831 | 11,222 | 280,212 | 5,123,891 | 912,259 | 1,700,708 |