Fig. 4
From: An efficient interpolation filter VLSI architecture for HEVC standard
Memory organization. Memory organization of the proposed architecture. The maximum processing unit of LPU is 64 × 64 block, and there are also four extra reference pixels around the processing unit. SRAM0–SRAM7 represent eight SRAMs in order to realize the storage of a 72 × 72 pixel matrix. The depth of every SRAM is 9 × 8 bit = 72 bits, and every bit is the data address of each line