EURASIP Journal on Advances in Signal Processing

Table 3 The new splitting module in interpolation filter

From: An efficient interpolation filter VLSI architecture for HEVC standard

PU module	The size of sub-PU
8×	8 × 8, 8 × 16, 8 × 32
16×	16 × 8, 16 × 16, 16 × 32
24×	24 × 32
32×	32 × 8, 32 × 16, 32 × 24, 32 × 32, 32 × 64
64×	64 × 32, 64 × 64

Based on the proposed fast interpolation algorithm

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